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Altera_Forum
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17 years ago

Timing analyzer and 1200mV 0C "fast" model

I keep getting violations (negative slack) in the timing analyzer on the 1200mV 0°C "fast" model, the other models are fine. These are the violations it reports: -0.055 0.078 0.184 0...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

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Minimum pulse width errors won't show up in the simulation. If d is coming from another domain, then at some time you will violate the setup or hold of the receive register, and that register will go metastable, so be sure your design handles that(add one or two more registers to de-metastabilize it). If you want the register to not go to X in the simulation, then in the Assignment Editor apply the setting "Show X on Violation" to Off for that register.

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Ok, so it is possible for a register in an FPGA to store a value that is neither 0 nor 1?