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Altera_Forum
Honored Contributor
17 years agoLooking at this simulation, I'm not even sure it is a problem. A pulse on input d is guaranteed to last a long time (more than a few clocks) and since signals never go unkown in a real device, if d is incorrectly read at the first clock after a state change on d, it'll just be processed correctly one clock later, which is a non-issue in this application as I have more than enough resolution in my clock rate vs the d signal.
It does serve as a reminder to oversample signals like this enough to not miss a pulse.