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germano's avatar
germano
Icon for New Contributor rankNew Contributor
3 years ago

Timing analysis - Timing requirements not met

Hello, When compiling my project I get two critical warning errors : 1. Critical Warning (14997): The FPGA to HPS SDRAM PLL reference clock path is not timing analyzed and could be subject to ji...
Nurina's avatar
Nurina
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,


We do not receive any response from you on the previous reply provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution, give Kudos and rate 4/5 survey


Regards,

Nurina