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germano
New Contributor
New ContributorTiming analysis - Timing requirements not met
Hello,
When compiling my project I get two critical warning errors :
1. Critical Warning (14997): The FPGA to HPS SDRAM PLL reference clock path is not timing analyzed and could be subject to ji...
Nurina
Regular Contributor
Regular ContributorHi,
What device are you targeting and what Quartus version are you using?
Can you share a screenshot of the clock connections in RTL viewer?
Regards,
Nurina
