Timing analysis - long combinational path

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I try to compile the standalone module with 150mhz clock, seems like there's no problem and timing pass check below:

In your big design, could you try set that module as design partition? Or logic lock. So it wouldn't be affected by other module

Go to Assignments -> Settings -> Compiler Settings and change the optimization mode to Performance (Aggresive). This settings helps also check:

Can try to run seed sweep as well

Hi, I am running Lite, so logic lock is not supported, but I just ran DSE. 

Hi, I am running Lite, so logic lock is not supported, but I just ran DSE. Summarized

+------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Exploration Summary ; +-----------------+--------------+--------------+---------------+--------------+------------------+-----------------+-----------------+----------------+ ;Exploration Point;Quality of Fit;f(MAX) Geomean;WC Slack: Setup;WC Slack: Hold;WC Slack: Recovery;WC Slack: Removal;Logic Utilization;Compilation Time; +-----------------+--------------+--------------+---------------+--------------+------------------+-----------------+-----------------+----------------+ ;dse1_1 ; 5.440;265.215 MHz ; -0.535; -0.104;No Data ;No Data ;32,674 ;00:05:34 ; ;dse1_2 ; 5.410;251.797 MHz ; -0.574; -0.104;No Data ;No Data ;32,679 ;00:05:42 ; ;dse1_3 ; 5.260;275.383 MHz ; -0.710; -0.104;No Data ;No Data ;32,613 ;00:05:42 ; ;dse1_4 ; 5.080;250.490 MHz ; -0.892; -0.104;No Data ;No Data ;32,602 ;00:05:22 ; ;dse1_base ; 5.460;254.045 MHz ; -0.510; -0.104;No Data ;No Data ;32,619 ;00:05:41 ; +-----------------+--------------+--------------+---------------+--------------+------------------+-----------------+-----------------+----------------+

What does fmax geomean, mean? All of them have setup/hold violations....

Which one is the best slack? Could share the report?

I downloaded Prime Standard and tried logic locking all 16 filter-instances in the same logic lock region. This caused the fmax to drop to 125MHz. Would it be better to have separate logic lock regions for all the filters?

I think you can try separate logic lock.

Btw, could you try to add register like below:

i_coef_data_s1 <= i_coef_data; --qng

mult_Re <= std_logic_vector(resize(signed(sample_in_s1) * signed(i_coef_data_s1(31 downto 16)), mult_Re'length)); --qng

mult_Im <= std_logic_vector(resize(signed(sample_in_s1) * signed(i_coef_data_s1(15 downto 0)), mult_Im'length)); --qng

This to pack into dsp

d_factor_s1 <= i_config_d_factor_reg; --qng

d_factor <= d_factor_s1; --qng

Register d_factor

--accRAM_Re_in_s1 <= accRAM_Re_in; --qng

--accRAM_Im_in_s1 <= accRAM_Im_in; --qng

Comment out these two.

Also use the Assignments -> Settings -> Compiler Settings -> Optimization mode: Performance (Aggressive)

The timing improved from slack 1.4ns to 2.2ns check:

Sorry for slow response... I will try it out...

Hi, I am running Aggressive Performance, but it did not help much.

I have also tried the filter with your suggested changes, which did not improve the Fmax.

I tested with separate Logic Lock regions, and I got the same result. Fmax = 125MHz.

Yesterday I tried adding multicycle-paths based on violation-report in the TIming Analyzer. Rerunning TA after adding mc-paths one-by-one showed improvements in the Fmax. I reached an Fmax of 140MHz. But, when I included the same statements in my constraints file and rebuilt the design I got more violations, related to other parts of the design, than I have gotten in a long time. How can this happen?

Hi,

May I know what is in your design? Possible remove other module first and compile the filter module first then lock the timing pass filter module. After that slowly add on other module

The processing pipeline consists of 16x filters, beamforming, scaling and fixed2float-conversion + 16x M9K sample-buffers. In addition config-register-bank, 16x pwm-transmitter + timing-controller and MCU-interface controller.

I will try adding module-by-module...

Hi, I have added another clock to the system and I am now running my processing pipeline on 120MHz. This clock is generated from the same PLL as the 150MHz. I now get an Fmax-report saying 122MHz and 149,19MHz, which is very close to what I need (120/150MHz). CDC is handled in the code, but not yet described/constrained properly in the sdc-file.

I get a number of violations, with my current sdc-file. Adding this statement in the Timing Analyzer:

set_clock_groups -logically_exclusive -group [get_clocks {pll_4x_output_1|altpll_component|auto_generated|pll1|clk[0]}] -group [get_clocks {pll_4x_output_1|altpll_component|auto_generated|pll1|clk[1]}]

....reduces the number of violations to only 3. But, if I include the very same statement in the sdc-file and rebuild the design, I get a lot of violations again. How can this be?

May I know the violation at the cdc path?

Could you try set clock group asynchonous in timing analyzer?

Hi,

These are the violations I get when I run:

set_clock_groups -asynchronous -group [get_clocks {pll_4x_output_1|altpll_component|auto_generated|pll1|clk[0]}] -group [get_clocks {pll_4x_output_1|altpll_component|auto_generated|pll1|clk[1]}]

report_timing -setup -npaths 1000 -detail full_path -panel_name {Report Timing} -multi_corner

Or, do you want me to run a specific CDC-path-report? Are they only supported in the PRO-version?

Fmax for 120/150/3/1.2 MHz

But, are the 120 and 150 MHz really asynchronous when they are generated by the same PLL?

Including the same statement in the constraints-file, gives 64 violations 

and an Fmax of

May I know the remaining violations are cdc? Could you show the launch and latch clocks?

Hi, my last build has only these violations, not related to CDC. The registerbus is running on 150MHz

I am looking into how to insert pipeline-registers in the bus.

hi, do you also have an answer to my questions?

what happen if adding register in between those two nodes?

I have tried to insert registers, but it ruins the bus-timing. I do not understand what the best way of inserting registers between the nodes. Do you have any suggestions on how to attack the challenge? 

Address-bus is 20 bits and data-bus is 16 bits, but address and data-bus is combined for bits (15:0).

Also, I do not see how addr-bit #10 is related to data-bit #15....

The slack seems quite close already. Could you try seed sweep any helps?