Timing analysis - long combinational path

A few things.

You have way too much logic in your state machine.  The next state logic should simply determine the conditions for switching state (determined in separate processes or elsewhere) and specify what the next state should be.  Setting outputs in particular states should be in their own separate non-clocked process so the appropriate output appears as soon as you move to the new state.  If you're reliant on some logic within a state to then determine a new value before then assigning an output, that's going to cause timing issues.  Create additional states to give yourself extra clock cycles or pull that logic out.  Assignments like these that rely on other logic within the same filtering state are probably the issue and should be in separate combinatorial processes:

accRAM_Re_in <= std_logic_vector(signed(add_Re_in) + signed(accRAM_Re_out_add));

accRAM_Im_in <= std_logic_vector(signed(add_Im_in) + signed(accRAM_Im_out_add));

Sticking to_integer and signed functions in there doesn't help matters either.