Timequest(SDC): constraining posedge launch negedge latch

Yes, clock constraints will do this. Note that derive_pll_clocks calls out create_generated_clock, so in essence they're the same thing. (If you go to TimeQuest messages, there will be one that says something like "Derive PLL clocks" and then it will show every create_generated_clock it calls, in the correct format. So there's really no difference.

I was showing with two clocks, but your case just has one. It's fine to have two always statements, one with posedge and one with negedge. Just constraining that single clock will get you half-cycle setup relationships when doing opposite edge transfers. Also, glad you like the TQ User Guide.