Timequest(SDC): constraining posedge launch negedge latch

First, thank you very much for the quick reply Rysc!

I think you're saying that the create_clock constraint is enough to constrain my design.

You've mentioned on your document that i can create_generated_clock in place of the derive_pll_clocks, so i can then do that to follow your clk_A example, since the clock i'm using comes from a PLL.

What confuses me is your clk_B statement. How do i relate that clock within the design if my code is referencing to the same signal? Like:

always @(posedge pllclkout)

....

always @(negedge pllclkout)

...

Would recoding it like below help, just so i can reference to a different node/signal on my SDC??? Just unsure if Quartus will delete the node name..

always @(posedge pllclkout)

....

assign pllclkout_neg = !pllclkout;

always @(posedge pllclkout_neg )

...

Just wanted to add a BIG THANK YOU for the document you've made! It has helped me a lot! More exposure/experience needed though. :)