Timequest(SDC): constraining posedge launch negedge latch

Just constraining your clocks does this.

create_clock -period 10.0 -name clk_A [targetA]

create_clock -period 5.0 -name clk_B [targetB]

(Target is just a place hold for the port or PLL output that creates the clock. The default of create clock is a 50/50 duty cycle, so all falling edge registers are clocked halfway in the period.

So rise -> fall transfers in clkA -> clkA would have a 5ns setup relationship

clkB(rise) -> clkB(fall) would have a 2.5ns relationship

clkA(rise) clkB(fall) would have a 2.5ns relationship. (Launch at 0, latch at 2.5)

clkB(rise) -> clkA(fall) would have a 5ns relationship (launch at 0, latch at 5)

There would be similar relationships with fall -> rise.

If your circuit is designed to transfer over different edges, then multicycles would adjust those.

Note that by just creating two clocks, 16 different relationships are created. All combinations of r/f, i.e. rise -> rise, fall -> fall, rise-> fall, fall -> rise. That's 4. These relationships occur in both directions, clkA -> clkB and clkB -> clkA, so that's 8. Then there is a setup and hold for each one. That gets it to 16.

In most cases, the clocks are the same period, 50/50 duty cycle, and so most of those relationships are the repeated, but under strange relationships they can all be different too.