Honored Contributor
Honored ContributorHey thanks for the quick reply! That clears up my confusion with that. I think a section on source synchronous would be greatly appreciated :)
I did have another question: I have a lot of places where a base clock coming into the fpga is connected to an output pin for a source synchronous interface. How do I specify this in the sdc file? Note - the output pin is simply connected to the input clock, it is not a ripple clock or a pll output. Should I create a generated clock on this port? As a follow-up to this, I also have some ripple clocks that are ouput from the FPGA and I have generated clocks associated with them in the sdc file, however when I run a report unconstrained paths, it reports the clock output pin as unconstrained, although it does mention that the port has a clock assignment. Do I need another constraint for this output clock pin?
