Honored Contributor
Honored ContributorOk, I think I understood well, but I read the datasheet for Marvel and it's really written badly - no options for timings, so I guess it has to be like this (btw, this is GMII interface, not RGMII - it doesn't trigger on both edges). However, setup and hold times are fairly loose, so I just needed to know how to constrain them in TimeQuest.
The I/O buffer I was talking about is the delay of the FPGA I/O pin itself + interconnect delay to it (and it ain't little - ~2.5 ns, maybe even 3 ns), so I was thinking I can use create_generated_clocks and constrain the real output clock and data with set_output_delay. This way, Quartus can make sure that external timing constraints are met. The PLL is another thing. As I said, I have a PLL generating clk125 and clk125_p90. Ok, so we have 90 deg phase shift between. The problematic part is that both of these two clocks are fed to Nios (MAC) and PHY through 2to1 muxes (because in GMII mode, for TX lines, PHY is producing 10/100 clocks, while MAC is supposed to generate 1 Gbit clock back to the PHY). Now, constraints for my analysis should start after these muxes (interconnect delay could kill the phase shift, or make it bigger), so that everything should be ok. I think I've got it. I'll give it a go tomorrow, and I'll post back if something's wrong. Thanks guys.
