Timequest Timing constrain Problem: Where can I get the PLL clock delay

Hello,

I'm working on a project that receive HDMI video on one end, re-scale it then output it on the other end.

but I have a problem, I don't know where to get the value of TX_CLK_TO_FPGA_min/max, please refer to the figure below.

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HDMI Receiver: ADV7611

HDMI Transmitter: ADV7513

FPGA: CYCLONE V C7D6

http://www.alteraforum.com/forum/attachment.php?attachmentid=12920&stc=1

Question: Where can I find the delay for clock TX_CLK_TO_FPGA_min/max?

Since it is generated by PLL, but I need a value to complete the formula.

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Here is the ADV7513 TX Timing:

http://www.alteraforum.com/forum/attachment.php?attachmentid=12922&stc=1

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Here is the ADV7611 RX Timing:

http://www.alteraforum.com/forum/attachment.php?attachmentid=12923&stc=1

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Here is the SDC script:

# **************************************************************#  Time Parameters# **************************************************************
# -----------------------------------------# ADV7611# specify the maximum clock-to-out of the external device
set tCO_RX_max 0.300# specify the minimum clock-to-out of the external device
set tCO_RX_min -2.200
# -----------------------------------------# ADV7513# specify the maximum setup time of the external device 
set tSU_TX 1.0# specify the hold time of the external device
set tH_TX 0.7
# **************************************************************#  RX Time Information# **************************************************************
# create the input clock
create_clock -name CLK_RX -period 6.734 # create the associated virtual input clock
create_clock -name CLK_RX_virt -period 6.734
# ----------------CLK_RX delay---------------------# ----clock delay is included by tco----# create the input delay referencing the virtual clock
# NOT EXIST IN ADV7611 DATASHEET# specify the maximum external clock delay from the external device
set RX_CLK_TO_HDMI_RX_max 0.0# specify the minimum external clock delay from the external device
set RX_CLK_TO_HDMI_RX_max 0.0
# specify the maximum external clock delay to the FPGA
set RX_CLK_TO_FPGA_max 0.200# specify the minimum external clock delay to the FPGA
set RX_CLK_TO_FPGA_min 0.100
# ----------------board_delay_in---------------------# specify the maximum board delay
set BD_RX_TO_FPGA_max 0.180# specify the minimum board delay
set BD_RX_TO_FPGA_min 0.120
# **************************************************************#  TX Time Information# **************************************************************# create the output clock# create_clock -name CLK_HDMI_M_OUT -period 6.734 
create_generated_clock -name {CLK_TX} -source .output_counter|divclk}] -master_clock {u0|pll_vid_m|altera_pll_i|cyclonev_pll|counter.output_counter|divclk}  
# ----------------CLK_TX delay---------------------# CAN NOT FIGER IT OUT# specify the maximum external clock delay to the FPGA
set TX_CLK_TO_FPGA_max unknow# specify the minimum external clock delay to the FPGA
set TX_CLK_TO_FPGA_min unknow
# specify the maximum external clock delay to the external device
set TX_CLK_TO_TX_max 0.100# specify the minimum external clock delay to the external device
set TX_CLK_TO_TX_min 0.050
# ----------------board_delay_out---------------------# specify the maximum board delay
set BD_FPGA_TO_TX_max 0.180# specify the minimum board delay
set BD_FPGA_TO_TX_min 0.120
# **************************************************************#  Set RX Input Delay# **************************************************************
# create the input maximum delay for the data input to the# FPGA that accounts for all delays specified
set_input_delay -clock_fall -clock {CLK_RX_virt} -max   HDMI_RX_HS HDMI_RX_VS HDMI_RX_DE}]
# create the input minimum delay for the data input to the# FPGA that accounts for all delays specified
set_input_delay -clock_fall -clock {CLK_RX_virt} -min   HDMI_RX_HS HDMI_RX_VS HDMI_RX_DE}]
# **************************************************************#  Set TX Output Delay# **************************************************************
# create the output maximum delay for the data output from the# FPGA that accounts for all delays specified
set_output_delay -clock CLK_HDMI_M_OUT -max   HDMI_TX_HS HDMI_X_VS HDMI_TX_DE}]
# create the output minimum delay for the data output from the# FPGA that accounts for all delays specified
set_output_delay -clock CLK_HDMI_M_OUT -min   HDMI_TX_HS HDMI_M_VS HDMI_TX_DE}]

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I write a sdc script base on "Altera Timequest Cookbook". I also read this wiki but I don't think it's completely correct. http://www.alterawiki.com/wiki/constrain_spi_core

http://www.alteraforum.com/forum/attachment.php?attachmentid=12921&stc=1