TimeQuest Timing Analyzer[Setup slack analysis]

I own TimeQuest maintenance and development now, although I did not design TimeQuest.

rbugalho is generally right in this thread. The Th, Tco, Tsu params are refecting real circuit delays, more precisely, relative delays between two ports on the register circuitry.

The documentation clearly states how these params are used in the equations. And the values can be positive or negative, depending on the HW design.

My team is SW and do not modify the model delay values from the ICDesign teams without very good reasons; and we have no good reasons to make these params positive.

Of course, model bugs appear all the time, so we appreciate the users reporting perceived problems. But the micro params on these registers, since they are so visible, have been scrutinized heavily by the SW and HW modeling teams (for mature FPGA products) and should be correct by now.

Chris Wysocki