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Honored Contributor
Honored ContributorTimeQuest Timing Analyzer[Setup slack analysis]
HI, I am trying to understand how the Time Quest analyzer calculating required setup and hold time.I have written code for register and the clocks are common(50 MHz). As per my understanding da...
Altera_ForumHonored Contributor
Honored Contributorok we are talking same about the same issue! the tSU of an FF is what altera calls micro tSU and xilinx calls it register tSU. It is is that window at ff ports.
If we are not interested at ff level e.g. we are looking at io pins then we only care about the window at pin level. So it is simply a relative issue. In FPGAs micro tSU is always positive by convention and tSU viewed anywhere in front is no longer called micro but just tSU e.g. from source register perspective or pin perspective.
