TimeQuest Timing Analyzer[Setup slack analysis]

Setup and hold times are defined at the pins, relative to the clock edge.

But they don't actually have to be both positive.

That actually depends on the internal circuit design of the flip-flop and how the delays add up at the transistor level.

You can have FFs with positive Tsu and positive Th, meaning the sensitivity window begins before the clock edge and ends after the clock edge.

You can have FFs with positive Tsu and negative Th, meaning the sensitivity window begins and ends before the clock edge.

This is actually the prevalent type of flip-flop design in integrated circuits today.

I lack the knowledge to explain properly how they're designed like this, but I'm looking at the design kit for a fairly recent process node for a well known foundry right now.

The flip-flops all have negative hold times and I don't see any wasteful delays inside the flip-flop circuits.

You can also have FFs with negative Tsu and positive Th, meaning the sensitivity window begins and ends after the clock edge.

I've never seen one out in the wild, but I've see papers describing the design.