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I think from a pure model of a register, where there is no clock or data delay to the register just the intrinsic feedback path, the uTsu is always a positive number that should be subtracted from the Data Required Path. That being said, it is not always modeled that way and clock or data delays near the register can be included. In both situations, the slack calculations will be the same, as you don't use uTsu as a value by itself, but as part of a calculation, and if some of the clock/data path is rolled into the uTsu number, it is taken out of the Data Arrival/Required Path. So in the end the slack calculation is correct, although looking at specific numbers may be misleading.
(A similar one I've seen in Stratix V is with an M20K unregistered output. When the M20K is the source of a critical path, the access time is really small, less than 100ps, which is amazing for a RAM access. But on the flip-side the path's clock skew is -1ns, which is terrible. What's really happening is some of the RAM access time is modeled as clock delay. I'm not sure the reasoning behind this, but the slack calculation is correct in the end).
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tSU of a register(so called micro Tsu) as well as micro tH are always positive by defintion. They can only change sign if the perspective changes e.g. to pins or another source register. But the equation clearly states micro tSU. So there ought to be something wrong here.
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