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don't sample on rising edge at one end and falling edge at other end. This will reduce setup relationship to half. apply same edge and don't worry about delays. That is the job of fitter , not the user.
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Ok, I've changed the design again. Now I have only rising edge-clocked registers in the entire design, which are loaded when the corrisponding enable signals are active.
The timing simulations are now consistent and the design also meets the timing requirements :)
The conclusions of this thread could be:
- preferably use enabled registers instead of using an asynchronous load signal;
- choose either a rising edge clock or a falling edge one for the design, then let the fitter do the job of avoiding race conditions.
Thank you all for your support.
Honored Contributor
