[TimeQuest] Some asynchronous signals detected as clocks

Ok, now I see clearly how this structure works. Thanks TCWORLD.

Meanwhile, I've changed my design, so now it uses those problematic registers with the main clock signal as their clock input and the asynchronous signal (the old asynchronous load) at the enable input. However, I've set these registers to work on the falling edge of the clock; this because the FSM changes state on the rising edge of the main clock and I considered some data delay for the enable signal (Moore output of FSM) to arrive at the registers. With this solution I managed to analyse the timing requirements on TimeQuest without unconstrained warnings for clocks.

Now I have strange results, that is a Launch-Latch clock relationship of 0 ns for the Hold Slack and a negative relationship of -5 ns for the Removal Slack. I'm guessing that TimeQuest isn't able to analyse a design where are both registers which work on the rising edge of the main clock and other ones which work on the falling edge, is this right?