TimeQuest slides

Is the OR gate being used to turn the clock on/off(i.e. is DATA_A held at a level for long periods), or is it used to just slow down the clock(so DATA_A is a periodic function)? What is the clock rate of CLK? What rate do you want S_CLK_OUT to be? Right now you're going to have a runt pulse, most likely. For example, if the register is outputting a 1, DATA_IN is at 0, then when the clk goes from 0 -> 1, the S_CLK_OUT will go high momentarily(from the CLK path through the OR gate), but shortly after the register will toggle low and drive it low. So you'll get a short pulse. This may be acceptable at the A/D, but is it what you want?

What device are you using? Is CLK on a PLL? If you have access to a PLL it makes it much easier. If just creating a slower speed clock, try to use another output of the PLL, or just divide down a register and have that go off chip(don't have a combinatorial gate being sent off chip as a clock.). If you're using the enable to turn the clock on and off(which usually isn't necessary for an A/D, I believe), then have the PLL output drive an ALTCLKCTRL megafunction. This is the mux used to get onto the global, so the PLL drives them anyway without being instantiated, but by manually adding it you have access to the enable port, allowing you to turn on and off your PLL output. (I can probably help more depending on your answers...)