TimeQuest: set_max_delay constraint

Technically, I still think you want skew. If the data enable goes through two delay registers before enabling the destination register to accept the data, what if the source data register had clock skew that was greater than two clock periods? (Or data delay AND clock skew that was greater than two clock periods.) Then the destination register would latch in the wrong data.

Of course, you could say that you know the clock skew is way too low for that to happen, but in that case it doesn't matter that clock skew is measured in, since it's a low number.

Regardless, I'm pretty sure there is no way to just do a point to point requirement between two registers. But as I type it, and if it's pretty easy to meet timing, you could constrain it(or not) with set_max_delay, and then your analysis script could use report_path, which does report what you want, it just doesn't constrain the fitter. You could put it in a panel and check it after each compile, or put a warning out if it fails with an equation. I think you can use post_message -warning "blaa blaa blaa" or something like that.