TimeQuest: set_max_delay constraint

One point on Brad's comment above, the set_max_delay and set_min_delay do use clock skew in their calculations. (Basically, all they do is override the launch and latch edge times for your setup and hold analysis. So set_max_delay of 10.0 will override that path so the launch edge is at 0.0 and the latch edge is at 10.0. The clock delays to the destination registrs is then used.

For the second post, it sounds like clock skew is important. If the skew to the clock on data was 3 clock cycles, then your enable would occur before the data did.

Note that I don't get the Edit: comment, that you don't want a fixed number. Are you saying you want Quartus to figure out how many delay elements you pass the enable through and apply a delay requirement for that? Or just that you will change the value for different parts of the design, which is doable, you just have to apply the constraint between registers and not clock domains.