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Altera_Forum's avatar
Altera_Forum
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13 years ago

TimeQuest set_false_path

Hi, I've tried to constrain my project in timequest. One register in design is clocked by 200 Hz, so i decided not to constrain this clock, but use set_false_path SDC command.

set_false_path -from [get_pins {Gen|clkA|regout}] -to [get_pins {Diagn|regA|clk}]

regA is the only register, which accept clock clkA as clock (there are some registers that accept this signal as data).

After full compilation i have warning

"Warning: Node: Gen:GenH|clkA was determined to be a clock but was found without an associated clock assignment."

Why does it happends, i cut all path for clkA as clock from timing anlize? And how i can fix this warning without createnig constrain clkA?

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    In that case, the tool needs clkA to be defined anyway.

    However even for very slow clock setting false path is not right.

    At such speed I don't expect setup violation but hold violation is likely
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I should also add that if you only have one register clocked by clkA then the tool cannot check that register unless the data input is either from another register or from constrained input pin

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    There's a catch there.

    At 200 Hz, they clock period is too big for TimeQuest to handle (it uses 32 bit numbers to represent time)

    You'll need to lie to TimeQuest a bit and constraint the clock for a frequency of at least 1 kHz.