Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Timequest SDRAM input: unconstrained and working vs closed and broken

https://alteraforum.com/forum/attachment.php?attachmentid=14800&stc=1 Hi folks, I have an interesting problem that I'm failing to make headway with. I'm working on a Cyclone V design (DE0-CV p...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

I managed to figure this out in the end and the SDRAM timing was rather misleading. It was actually due to the use of an combinationally derived asynchronous reset derived on the prefetch FIFO and different placements could either cause that glitch to be present or hidden, so I'm happy now :)