TimeQuest RGMII Problem

Rysc,

I have a related question you may be able to help me with. As I mentioned in my original post, I have two RGMII channels. One channel pretty much meets timing, but the other channel fails it's TX interface (the output from the FPGA to the PHY). In comparing the two channels, the one that passes has pretty low pin-to-pin skew for it's output data (.200 ns), where as the failing channel has much larger pin-to-pin skew (.575 ns). Also the skew between the clock and data on the passing channel is pretty tight where as on the failing channel it is not. These are all altddio outputs, including the clock, which I thought would give me very low skew between all of the output data pins and the output clock. Is there any way to tell quartus to make the skew between these output pins as low as possible (preferably the same)? It seems to me that low skew is more important in a source synchronous design than the actual delay. I think this is particularly true in my case, because the PHY can be programmed to skew the clock.