Timequest results differ from Modelsim

I think your observation is not right.

In Modelsim you are right to see directly and compare but you are comparing output clock not with internal clock but with copy of internal clock as seen on the pin which implies uncertain delays.

Moreover your timequest report dependancy for quartus is not right.

I suggest you ignore this issue. Instead get your timings right away from simulation. Frankly I never need to do gate level simulation but rather do functional rtl simulation and pass quartus timing.