Timequest results differ from Modelsim

Ok First there is one clock that is an output of the FPGA, This clock drives the ram, the ram then send data back to the FPGA, and then I use a second clock which is internal to the FPGA to clock in the data.

At the PLL, even though they are seperate outputs of the pll, The clocks currently have the same phase. I want to shift it to get better timing results.

In a SDC file i used a create_generated_clock command to create a clock on the output port of the FPGA. Then I constrained the I/O with set_input_delay min and max.... Then in Timequest I did a report_timing command on that ram data that is coming in. It has a launch clk = output clk. and a Latch clk = the pin of the pll. the difference between the two clocks is 0.2ns.

Then in modelsim, using the slow model netlist. I simulated the design. In the waveform I have the output clk, the output port of the FPGA, and i also have the pin of the PLL, or the internal clk. But the difference here is 2.2ns.

It just bugs me that modelsim has a different result.

how do you set resolution in modelsim. Can't you just set in the top testbench verilog file?

If I had the design on this computer i would do more copy and pasting and maybe do a screen capture, but the design computer doesn't have an internet connection for security reasons. but if you still need more information i can still copy the sdc and do some screen captures, it is just a hassle.