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Altera_Forum's avatar
Altera_Forum
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15 years ago

Timequest results differ from Modelsim

So In Timequest I have a launch clock and a latch clock for some data. The latch clock is about a 0.2 ns delay after launch clock. It modelsim using the slow model netlist, same as timeques...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I have a clock that drives an external ram. It's source is a port of the FPGA. I have another clock that clocks in the data. It's source is another pin of the pll. So they are two seperate clocks.

I am trying to figure out how to shift the second clock to get best results. But timequest and modelsim differ.