Timequest reports no constraining problems, hardware still not working

--- Quote Start ---

Hello,

the Stratix V Dev. Kit does have a cooler fan on the FPGA, so it shouldn't overheat.

And as I said, the only I/O for this system is clock, reset and jtag. They shouldn't affect the system timing in overall if not constrained, right?

Thanks for the quick answer.

--- Quote End ---

It is not about overheating but testing temperature effect by freezing and if it still fails try heating it with hot air. If design works in this test then it confirms timing issue as delays are changed by temp.

Other causes related to clk should be considered e.g. rate control, fifo overflowing etc...