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Altera_Forum's avatar
Altera_Forum
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11 years ago

Timequest reports no constraining problems, hardware still not working

Hello all, I have a Verilog module (coded in Bluespec) that was working in my Stratix IV Kit. This module internally uses pipelined LPM_DIVIDE. When I decided to migrate to Stratix V (5SG...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Hello,

the Stratix V Dev. Kit does have a cooler fan on the FPGA, so it shouldn't overheat.

And as I said, the only I/O for this system is clock, reset and jtag. They shouldn't affect the system timing in overall if not constrained, right?

Thanks for the quick answer.