Timequest relating an external clock input to a virtual clock

A better way to explain it would be like this. Take an input. A virtual clock is used to describe the clock driving the "upstream" device, essentially the source register. When you create your set_input_delay constraint, you have to point to this virtual clock. This ties the virtual clock as the source clock to whatever clock is driving the input register, the destination register, in the FPGA, whether it's a base clock (create_clock) or generated clock (create_generated_clock, derive_pll_clocks). Outputs are tied to virtual clocks with set_output_delay in a similar manner.