TimeQuest puzzle

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I am trying to learn TimeQuest and it's not going very quickly I'm afraid.

I have a little MAXII example I am trying to analyze with TimeQuest that is giving me fits. In this example, I am circulating data between an internal

and an external register using a generated external clock which is only output some of the time. In this simplified example, only every other clock is output to EXT_CLK, but more generally, I need to control EXT_CLK with more complex logic. I am using Quartus II 9.1.

Here's the Verilog:

-----------------------------------

module TimeQuestExample

(

input CLK,

output EXT_CLK,

input DATA_IN,

output DATA_OUT

);

reg data;

assign DATA_OUT = data;

reg toggle;

assign EXT_CLK = !CLK && toggle;

always @(posedge CLK) begin

toggle <= !toggle;

data <= DATA_IN;

end

endmodule

-----------------------------------

And here is the SDC file I am using:

create_clock -period 30 [get_ports CLK]

create_generated_clock -source [get_pins {EXT_CLK~0|combout}]

-master_clock [get_clocks {CLK}] [get_ports EXT_CLK]

set_input_delay -clock CLK 0 [get_ports {CLK}]

set_input_delay -clock EXT_CLK -clock_fall 8 [get_ports {DATA_IN}]

set_output_delay -clock EXT_CLK 7 [get_ports {DATA_OUT}]

------------------------------------------------------------------

When I run the timing analyzer, I get lots of unconstrained paths with

report_ucp. However, if I add the following constraint, all the issues just

go away.

------------------------------------------------------------------

set_output_delay -clock EXT_CLK 0 [get_ports {EXT_CLK}]

------------------------------------------------------------------

Can anybody help me understand why this works (if correct), or what would

be a better way to get the design fully constrained.

Thanks,

henderbc

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Hi,

without timing constraint Timequest did not check the timing of e.g. outputs. In your case you don't have a constraint for the output "EXT_CLK". When you look back from the pin into your design you found two paths ( EX_CLK -> CLK, EXT_CLK -> "toggle") which therefore are not constrainted. You also need the constraint in order to ensure that the DATA_OUT is correct latch with you EXT_CLK.

Kind regards

GPK

Hi GPK - thanks for you answer. What is still puzzling me is the meaning of the constraint:

set_output_delay -clock EXT_CLK 0 [get_ports {EXT_CLK}]

If I understand what set_output_delay is supposed to do, I would think this means:

"EXT_CLK will take a while to get to my external device so we better delay EXT_CLK by that much to make sure EXT_CLK is correctly latched at the external device by EXT_CLK"

This sounds like nonsense to me. What am I missing?

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Hi GPK - thanks for you answer. What is still puzzling me is the meaning of the constraint:

set_output_delay -clock EXT_CLK 0 [get_ports {EXT_CLK}]

If I understand what set_output_delay is supposed to do, I would think this means:

"EXT_CLK will take a while to get to my external device so we better delay EXT_CLK by that much to make sure EXT_CLK is correctly latched at the external device by EXT_CLK"

This sounds like nonsense to me. What am I missing?

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Hi,

a good explanation could be found in the Application Note AN433 helps:

http://www.altera.com/literature/an/an433.pdf?gsa_pos=1&wt.oss_r=1&wt.oss=an433

Kind regards

GPK

Hi GPK,

That helps a lot. I'm thinking the constraint I had was nonsense. I changed it to:

set_output_delay -clock CLK 1.23 [get_ports {EXT_CLK}]

which also makes the unconstrained ports and paths problems go away.

Is the above constraint now correct?

If so, what does it mean in English, and how should I calculate the delay value? (I just stuck in 1.23)

If not, how should it be written?

Thanks for your patience

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Hi GPK,

That helps a lot. I'm thinking the constraint I had was nonsense. I changed it to:

set_output_delay -clock CLK 1.23 [get_ports {EXT_CLK}]

which also makes the unconstrained ports and paths problems go away.

Is the above constraint now correct?

If so, what does it mean in English, and how should I calculate the delay value? (I just stuck in 1.23)

If not, how should it be written?

Thanks for your patience

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Hi,

the value depends on the requirements of the receiving device. Are the data latched in with the pos- or negedge ? What is the required setup time ?

Kind regards

GPK

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Hi,

the value depends on the requirements of the receiving device. Are the data latched in with the pos- or negedge ? What is the required setup time ?

Kind regards

GPK

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Hi GPK,

I'm not really too concerned about the value - I don't understand the meaning. Here's a picture that might simplify this discussion:

http://photosbybruce.smugmug.com/photos/749483837_kenbm-m.jpg

The constraints I entered for Quartus were:

create_clock -period 30 [get_ports CLK]

create_generated_clock -source [get_pins {EXT_CLK~0|combout}] \

-master_clock [get_clocks {CLK}] [get_ports EXT_CLK]

set_input_delay -clock EXT_CLK -clock_fall 8 [get_ports {DATA_IN}]

set_output_delay -clock EXT_CLK 2 [get_ports {DATA_OUT}]

These constraints give my intent for the design. But when I analyze the design with TimeQuest and output the report_ucp,

I get the following:

+---------------------+

; Unconstrained Paths ;

+---------------------+

+------------------------------------------------+

; Unconstrained Paths Summary ;

+---------------------------------+-------+------+

; Property ; Setup ; Hold ;

+---------------------------------+-------+------+

; Illegal Clocks ; 0 ; 0 ;

; Unconstrained Clocks ; 0 ; 0 ;

; Unconstrained Input Ports ; 1 ; 1 ;

; Unconstrained Input Port Paths ; 1 ; 1 ;

; Unconstrained Output Ports ; 1 ; 1 ;

; Unconstrained Output Port Paths ; 2 ; 2 ;

+---------------------------------+-------+------+

+---------------------------------------------+

; Clock Status Summary ;

+---------+---------+-----------+-------------+

; Target ; Clock ; Type ; Status ;

+---------+---------+-----------+-------------+

; CLK ; CLK ; Base ; Constrained ;

; EXT_CLK ; EXT_CLK ; Generated ; Constrained ;

+---------+---------+-----------+-------------+

+----------------+

; Setup Analysis ;

+----------------+

+--------------------------------------------------------------------------------------------------------------------------------------+

; Unconstrained Output Ports ;

+-------------+------------------------------------------------------------------------------------------------------------------------+

; Output Port ; Comment ;

+-------------+------------------------------------------------------------------------------------------------------------------------+

; EXT_CLK ; No output delay, min/max delays, false-path exceptions, or max skew assignments found. This port has clock assignment. ;

+-------------+------------------------------------------------------------------------------------------------------------------------+

+--------------------------------+

; Unconstrained Input Port Paths ;

+------+---------+---------------+

; From ; To ; To Clocks ;

+------+---------+---------------+

; CLK ; EXT_CLK ; CLK ;

+------+---------+---------------+

+---------------------------------+

; Unconstrained Output Port Paths ;

+--------+---------+--------------+

; From ; To ; From Clocks ;

+--------+---------+--------------+

; CLK ; EXT_CLK ; ;

; toggle ; EXT_CLK ; CLK ;

+--------+---------+--------------+

+---------------+

; Hold Analysis ;

+---------------+

+--------------------------------------------------------------------------------------------------------------------------------------+

; Unconstrained Output Ports ;

+-------------+------------------------------------------------------------------------------------------------------------------------+

; Output Port ; Comment ;

+-------------+------------------------------------------------------------------------------------------------------------------------+

; EXT_CLK ; No output delay, min/max delays, false-path exceptions, or max skew assignments found. This port has clock assignment. ;

+-------------+------------------------------------------------------------------------------------------------------------------------+

+--------------------------------+

; Unconstrained Input Port Paths ;

+------+---------+---------------+

; From ; To ; To Clocks ;

+------+---------+---------------+

; CLK ; EXT_CLK ; CLK ;

+------+---------+---------------+

+---------------------------------+

; Unconstrained Output Port Paths ;

+--------+---------+--------------+

; From ; To ; From Clocks ;

+--------+---------+--------------+

; CLK ; EXT_CLK ; ;

; toggle ; EXT_CLK ; CLK ;

+--------+---------+--------------+

Am I missing an important constraint? What do I need to change to make these unconstrained ports and paths go away?

Thanks,

Bruce

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Hi GPK,

I'm not really too concerned about the value - I don't understand the meaning. Here's a picture that might simplify this discussion:

http://photosbybruce.smugmug.com/photos/749483837_kenbm-m.jpg

The constraints I entered for Quartus were:

create_clock -period 30 [get_ports CLK]

create_generated_clock -source [get_pins {EXT_CLK~0|combout}] \

-master_clock [get_clocks {CLK}] [get_ports EXT_CLK]

set_input_delay -clock EXT_CLK -clock_fall 8 [get_ports {DATA_IN}]

set_output_delay -clock EXT_CLK 2 [get_ports {DATA_OUT}]

These constraints give my intent for the design. But when I analyze the design with TimeQuest and output the report_ucp,

I get the following:

+---------------------+

; Unconstrained Paths ;

+---------------------+

+------------------------------------------------+

; Unconstrained Paths Summary ;

+---------------------------------+-------+------+

; Property ; Setup ; Hold ;

+---------------------------------+-------+------+

; Illegal Clocks ; 0 ; 0 ;

; Unconstrained Clocks ; 0 ; 0 ;

; Unconstrained Input Ports ; 1 ; 1 ;

; Unconstrained Input Port Paths ; 1 ; 1 ;

; Unconstrained Output Ports ; 1 ; 1 ;

; Unconstrained Output Port Paths ; 2 ; 2 ;

+---------------------------------+-------+------+

+---------------------------------------------+

; Clock Status Summary ;

+---------+---------+-----------+-------------+

; Target ; Clock ; Type ; Status ;

+---------+---------+-----------+-------------+

; CLK ; CLK ; Base ; Constrained ;

; EXT_CLK ; EXT_CLK ; Generated ; Constrained ;

+---------+---------+-----------+-------------+

+----------------+

; Setup Analysis ;

+----------------+

+--------------------------------------------------------------------------------------------------------------------------------------+

; Unconstrained Output Ports ;

+-------------+------------------------------------------------------------------------------------------------------------------------+

; Output Port ; Comment ;

+-------------+------------------------------------------------------------------------------------------------------------------------+

; EXT_CLK ; No output delay, min/max delays, false-path exceptions, or max skew assignments found. This port has clock assignment. ;

+-------------+------------------------------------------------------------------------------------------------------------------------+

+--------------------------------+

; Unconstrained Input Port Paths ;

+------+---------+---------------+

; From ; To ; To Clocks ;

+------+---------+---------------+

; CLK ; EXT_CLK ; CLK ;

+------+---------+---------------+

+---------------------------------+

; Unconstrained Output Port Paths ;

+--------+---------+--------------+

; From ; To ; From Clocks ;

+--------+---------+--------------+

; CLK ; EXT_CLK ; ;

; toggle ; EXT_CLK ; CLK ;

+--------+---------+--------------+

+---------------+

; Hold Analysis ;

+---------------+

+--------------------------------------------------------------------------------------------------------------------------------------+

; Unconstrained Output Ports ;

+-------------+------------------------------------------------------------------------------------------------------------------------+

; Output Port ; Comment ;

+-------------+------------------------------------------------------------------------------------------------------------------------+

; EXT_CLK ; No output delay, min/max delays, false-path exceptions, or max skew assignments found. This port has clock assignment. ;

+-------------+------------------------------------------------------------------------------------------------------------------------+

+--------------------------------+

; Unconstrained Input Port Paths ;

+------+---------+---------------+

; From ; To ; To Clocks ;

+------+---------+---------------+

; CLK ; EXT_CLK ; CLK ;

+------+---------+---------------+

+---------------------------------+

; Unconstrained Output Port Paths ;

+--------+---------+--------------+

; From ; To ; From Clocks ;

+--------+---------+--------------+

; CLK ; EXT_CLK ; ;

; toggle ; EXT_CLK ; CLK ;

+--------+---------+--------------+

Am I missing an important constraint? What do I need to change to make these unconstrained ports and paths go away?

Thanks,

Bruce

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Hi Bruce

I have a project attached. Maybe it helps to understand how to solve your problem.

You have to define an output constraint for your EXT_CLK output.

Kind regards

GPK