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I am trying to learn TimeQuest and it's not going very quickly I'm afraid.
I have a little MAXII example I am trying to analyze with TimeQuest that is giving me fits. In this example, I am circulating data between an internal
and an external register using a generated external clock which is only output some of the time. In this simplified example, only every other clock is output to EXT_CLK, but more generally, I need to control EXT_CLK with more complex logic. I am using Quartus II 9.1.
Here's the Verilog:
-----------------------------------
module TimeQuestExample
(
input CLK,
output EXT_CLK,
input DATA_IN,
output DATA_OUT
);
reg data;
assign DATA_OUT = data;
reg toggle;
assign EXT_CLK = !CLK && toggle;
always @(posedge CLK) begin
toggle <= !toggle;
data <= DATA_IN;
end
endmodule
-----------------------------------
And here is the SDC file I am using:
create_clock -period 30 [get_ports CLK]
create_generated_clock -source [get_pins {EXT_CLK~0|combout}]
-master_clock [get_clocks {CLK}] [get_ports EXT_CLK]
set_input_delay -clock CLK 0 [get_ports {CLK}]
set_input_delay -clock EXT_CLK -clock_fall 8 [get_ports {DATA_IN}]
set_output_delay -clock EXT_CLK 7 [get_ports {DATA_OUT}]
------------------------------------------------------------------
When I run the timing analyzer, I get lots of unconstrained paths with
report_ucp. However, if I add the following constraint, all the issues just
go away.
------------------------------------------------------------------
set_output_delay -clock EXT_CLK 0 [get_ports {EXT_CLK}]
------------------------------------------------------------------
Can anybody help me understand why this works (if correct), or what would
be a better way to get the design fully constrained.
Thanks,
henderbc
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Hi,
without timing constraint Timequest did not check the timing of e.g. outputs. In your case you don't have a constraint for the output "EXT_CLK". When you look back from the pin into your design you found two paths ( EX_CLK -> CLK, EXT_CLK -> "toggle") which therefore are not constrainted. You also need the constraint in order to ensure that the DATA_OUT is correct latch with you EXT_CLK.
Kind regards
GPK
Honored Contributor
