Forum Discussion
Altera_Forum
Honored Contributor
10 years agoTimequest missing option for derived_pll_clocks
I don;t see -phase 90 option when I create a generated clock through Timequest for PLLs. In PLL IP, I pick 90 degree phase shift. I compiled the design. In fitter resource usage summary, I confirm th...
Altera_Forum
Honored Contributor
10 years agoIt should be there. Maybe under a different form (-waveform) ?
Can you show the section of exported sdc file (write_sdc -expand) ? Did you check the clocks report ?