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Why are so many paths not constraint ? Are that I/O or internal paths ?
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Most of them are I/Os but there are also some internal clocks. This design was designed for the stratix III with the classic analyzer. I've just recently upgraded to the stratix IV. With the classic analyzer, I've managed to get by without much worrying about constraints. The design worked. Now, I can't get the design to work despite the fact that I have a faster speed grade device.
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Do you have a look to the clock transfer results ?
Are all clock domain crossings properly designed ?
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The report says that there is one "false path". But these Clocks are not in any way involved in that section that I am observing the timing failures.
Honored Contributor
