--- Quote Start ---
Thanks for the reply. No, not all paths are constrained. But there are just too many according to the report, but most of them should not be relevant to the problem at hand. The clocks that are involved in the circuitry are constrained and are making timings according to the tool. The only thing I'm not sure about is how the Quartus II handles the enable pins of the registers that are toggled for controlling the data rate.
--- Quote End ---
Hi,
do you have different clock domains ? Do you have a look to the clock transfer results ?
Are all clock domain crossings properly designed ?
Why are so many paths not constraint ? Are that I/O or internal paths ?
Kind regards
GPK
Honored Contributor
