Forum Discussion

New Contributor

7 years ago

TimeQuest: How do I eliminate the clock delay through a PLL from my timing budget for external IO?

I've got the following related constraints: set_clock_groups -asynchronous -group {input_clk_40} \ -group {pll_output_clk_50|Frac_PLL(eg.)} -group {pll_output_clk_50|divclk} create_clock -name vi...

CBehr

New Contributor

7 years ago

I did some more experimentation and came up with an example. Please check out the following post:

https://forums.intel.com/s/question/0D50P000046JFY7SAO/problem-using-setmindelay-between-quartus-and-timequest-results-between-the-two-tools-are-inconsistent

Probably answer there. Thanks.

Forum Discussion

TimeQuest: How do I eliminate the clock delay through a PLL from my timing budget for external IO?

Recent Discussions

Timing analysis - long combinational path

Questa unable to checkout a viewer license

Crash at elaboration

Quartus did not start

Self service license server doesn't work