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OK - thank you. So assume my clock and data are have zero degrees of timing error when applied to the input pins of the FPGA I don't need any set_input delay then? If I want to sample in the middle of the data eye then I write FPGA code to do that.
But if they don't have zero degrees of timing error, say due to different PC track lengths, then can I use set_input_delay to compensate?
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No no...
you always need to tell the tool the io data/clock offset othrwise it has no way to "see" that offset. It only then decides timing at that register. So how could timing pass with no such knowledge?
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