--- Quote Start ---
In my example the clock and data are synchronous but within the FPGA I wish to sample the data at the middle of the clock period. In which case what set_input_delay settings do I use please?
--- Quote End ---
Your question is wrong. It seems you are thinking like this:
I got data and clock coming into fpga (their relation unknown) then I want first fpgs io register to sample it in the middle of clock period by inserting some delay and without knowing what is the received data offset from clock launch edge.
The purpose of set_input_delay is to give information to the tool about data clock offset
as received at io and you leave it to the fitter to insert a siutable delay and get timing right at io register. you can narrow down your offset if you want stricter control up to a limit but once the tool gets timing it does not care about positioning the data eye as you prescribe. There might be other absolute delay constraints so that you decide the delay rather than the tool but ultimately you want to pass timing rather than put data eye somewhere nice.
Honored Contributor
