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Hi Kaz,
Thanks for the feedback - much appreciated. Could you please suggest a simple example, that explains this issue, that we could include in the documentation.
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rather than examples one should be clear about the meanings (definitions), here is my understanding:
set_input_delay min is minimum data offset from its clock launch edge
max is maximum data offset from its clock launch edge
zero means data and clock aligned
so given tCO of input device and board delay then
min = min tCO, and max = max tCO of external device plus board delay effect at each path of data and clock from device to io
This is straightforward
set_output_delay min is minimum allowed offset of data from its clock latch edge, negative by convention
max is maximum allowed offset of data from its clock latch edge
i.e. transition allowed between min & max (but not between max &min)
zero means no requirement (but this is not realistic)
so given tSU/tH of external device and board delay then
min = -tH, max = tSU of external device plus board effect on both data and clock from io to device
This is not straightforward as it is not symmetrical in definition with set_input_delay due to negativity of min which apparently comes from min offset seen as after edge while max is before edge.
Honored Contributor
