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Hi,
I'm involved in an international open source Software Defined Radio project that uses Altera FPGAs (
www.openhpsdr.org (
http://www.openhpsdr.org/)). We are currently encouraging our members to contribute to FPGA development.
Many of our members are very experienced C/C++/C# programmers but have not been exposed to FPGA coding before. One issue we find is the steep learning curve for such programmers when starting to use Timequest.
In which case we have written a user guide, aimed at beginners, called "A standardized procedure for closing timing on openHPSDR FPGA firmware designs".
You can obtain a copy of the document here:
http://www.k5so.com/timingclosurefieldguide.pdf We would welcome peer reviews by experienced Timequest users in order to continually improve this document.
Regards
philh
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Obviously we are all not happy about the volume of Altera documentation on Timequest. However, One has to be careful writing or reading 2nd hand summaries or guides as it just adds to the pool of words and may have errors.
I skimmed a bit through your summary. I wasn't happy about your account of set_input_delay and set_output_delay as you imply you can just enter some arbitrary values and check if it is ok with timing report. These values have to be entered from physical relationship at your io between data and clock. The purpose is not just to get a clean pass but enter correct values + pass. The tool is not aware about io relatioship and needs your entry.
Honored Contributor
