Timequest default setup relationship through PLLs

Run Report Clocks. Something looks wrong with your 100MHz clock. The 300MHz launch edge is at 3.333ns, which is correct, but the latch edge is at 4.286 when it should be 0/10/100, etc.

Note that coming out of different PLLs, you may end up with a rounding issue, but that would result in a 1ps setup relationship(9.999ns to 10ns), and not what you're seeing. If that were to occur, you would need to add:

set_max_delay -from clk300 -to clk100 3.333

And why not have the 100MHz come out of the first PLL? I assume there is a reason you're not showing.