Honored Contributor
Honored ContributorNot really using a virtual clock to drive the source synchrounous outputs. It is generated off the DDR output register. I am driving these off a PLL output that is phase shifted 180 degrees. It is just a single edge sync output, so this is working good.
We are using the Quad Ethernet daughter board from MoreThanIP. The first port on the device is GMII, which is single edge at 125M. The next three ports are RGMII, which is DDR at 125M. Only using two of the ethernet ports. The first is working good, and the secon DDR port output is fine. Just having fun with the DDR input, since the clock input is not on a global clock bus. Can't use a PLL to phase shift the input. MoreThanIP has a solution. Just trying to get good enough at TimeQuest to know when I have the right answer. Thanks for your help.
