Honored Contributor
Honored ContributorThat's correct. If you invert the clock through DDR(by tying high register to GND and low register to VCC) then you need to apply the -invert to the generated clock. You also said that you're using a virtual clock, but for source-synchronous outputs you shouldn't use a virtual clock, but instead the generated clock that is applied to the output port. Finally, are you sending it edge-aligned(which means the same clock can drive the data and clock) or center-aligned(which means you need a PLL which creates two clocks, one for the data, and one phase-shifted 90 degrees for the clock)?
