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Altera_Forum's avatar
Altera_Forum
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16 years ago

TimeQuest Constraints

I have taken three of the Altera classes for timequest, and it still is not very clear. I have a synchrounous DDR input with both the data and clock aligned with matched lines from the output chip. N...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Thanks for your help on timequest. I always seem to have more questions.

I have a source synchrounous output design. The data output is setup to be in I/O registers, and the clock source is generated using a DDR output, so it is also registered in the I/O. These should line up rather nicely on the data output. The output clock is setup as virtual, and it shows up in the timequest clock report. I can provide a design or pictures if you want. However, my question is fairly simple.

The hold/setup results do not make sense to me. Assume a 100MHz clock. The hold results use 0ns for both the start of the data arrival path and the data required path. The setup results use 0ns for the start of data arrival path and 5ns for the data required path.

If I invert the output clock the setup/hold results do not change. What am I missing?