TimeQuest Constraints

THis might help(yes, it's a lot,but it has examples)

http://www.alteraforum.com/forum/showthread.php?t=4806&highlight=source-synchronous

1) You definitely want to use a virtual clock. Note that your set_output_delay -clock was the PLL output, which is definitely wrong. THis will be timed with all the delay to and thru the PLL, but it will be as if it magically leaves the chip from there with no delay and drives the external device. There's a warning about this, which I personally think should be an error. (Users make this mistake all the time. The big thing is that the -clock doesn't describe the clock in the FPGA, as TimeQuest already knows this, but the clock that drives the external device)

2) On the input side, the clock drives the DDR input clock directly. You need it to go through a PLL, and have that PLL set up in source-synchronous compensation mode.

3) The attachment in the link has examples I would suggest looking at. I made a quick pass to get you started. Note that:

I made the -waveform on the virtual clock be shifted 90 degrees. This basically means that the clock and data lines inside the FPGA should be as close to equal as possible to keep the clock edge in the middle of the data window. I'm assuming that's what you want since you're not shifting the clock.

I made the input and output delays 0ns, which is as least restrictive as possible(and impossible). Basically the setup and hold requirements are half a data period, or 2.5ns each. You want to expand the external delays to say how much skew is out there. For example, if the external device sending data could skew the data to the clock by +/-1ns, then make the -max 1.0 and the -min -1.0.