Timequest constraints for SRAM

Virtual Clock is not a real physical clock; it is only a way to tell TimeQuest what IO requirements you have. So you could definitely define a virtual clock without a port associated to it. Study the user guide more thoroughly. There are lots of examples. None of them may be exactly what you need, but there are basics that you can modify.

If a clock never leaves the FPGA, something is wrong with your design. Find the bug and correct it. Ensure it has not been optimized away.

For set_input_delay & set_output_delay you need a virtual clock, not a real physical clock.