Timequest constraints for SRAM

Thank you for your answer,msj.

I read all the documents availible at Altera web site and I didnt find any example that is similar to my design.

All the SDR interface examples use a same clock for internal logic and for RAM clk pin. In my case, clock that drives an external RAM comes from PLL, and in terms of timequest it is a different clock.

There are number of advantages in using ext. feedback PLL:

1) Phase alignement between clocks of internal logic and external chip

2)My board is exposed to extreme cold/heat. Trace length and conductivity changes in such conditions. External feedback alows to compensate these changes and keep the interface aligned.

I cannot use virtual clock for output delay constraint.

I cannot use and internal clock, because PLL doesnt compensate a path from last FF to FPGA PAD (clock never leaves FPGA).

I cannot use a clock from ext. fb. Pll because timequest doesnt see any relationship between this clock and data/address pins.