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Altera_Forum
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17 years ago

Timequest constrains for async SRAM

Any samples about how to constrain an async SRAM interface? Timequest doesn't seem to support the required constrains. For reading, you need the sum of tCO and tSU, and for writing you need dat...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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Here is the example that Godfather was referring to. It is part of a document that we are putting together on TimeQuest solutions. I believe this covers the exact situation that you are trying to constrain. It even has a Quartus archive of a test case embedded in the document. Hope this helps.

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Hi, jimbo.

I found the attached file "Async RAM Example". It is helpful to me. However, it is a part of some document. I tried to find the document but can not find it. Would you please tell me how to get it? Thanks.