Timequest constrains for async SRAM

If I'm not confusing this with something else I was told, delay chains are set by the Fitter early in the Fitting process using course timing estimates. (The Fitter runs timing analysis in the background. For some things it does a quick analysis that isn't as precise as when timing analysis is run at the end.)

Whenever I want an I/O bus to have timing as similar as possible across the bus, I manually set the delay chains through the Assignment Editor. I might let the Fitter pick the settings first to get an idea what is a good value to try for my initial manual setting. I also make manual assignments to force usage of I/O cell registers. Letting the Fitter decide whether to use I/O cell registers based on timing can result in only some bits in a bus using them.