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Speaking about output enable, I realized that this is not constrained. I spent quite some time browsing Quartus handbook, and I couldn't find any reference whatsoever about how to constrain the high-Z and low-Z timing. Actually, I cannot even find these timing in the device datasheets at all!
Without any information, I can only assume the low-Z timing is similar to the micro tCO of the I/O element?
But even then, how can I associate the node that control the OE to the actual data nodes? Or at least how can I get a timing report for the OE node?
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The output enable path will be reported if the data port is constrained by either set_output_delay or set_max_delay. Run report_timing with a data port in the -to field. With a high enough number for -npaths, you will see the paths for both the data register to data port and the output enable register to the data port.
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